About the Role

We are looking for a Senior VLSI Design Engineer to take a leading role in the development of advanced DSP cores and hardware accelerators. In this hands‑on position, you will own the full design flow — from architecture and micro‑architecture definition, through RTL development and verification, to synthesis, timing closure, and STA.
Your work will directly influence the silicon success of next‑generation products across multiple domains.

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Key Responsibilities

• Lead end‑to‑end design and implementation of advanced digital IPs, including DSP cores and hardware accelerators.
• Define architecture and micro‑architecture for complex digital blocks.
• Perform RTL design using Verilog/SystemVerilog.
• Work closely with verification teams to ensure design quality.
• Conduct synthesis, timing closure, and static timing analysis (STA).
• Collaborate with cross‑functional teams to deliver high‑quality silicon.

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Requirements

Must-Have:

• B.Sc. or M.Sc. in Electrical Engineering
• 5–10 years of experience in VLSI design
• Strong proficiency in RTL design (Verilog / SystemVerilog)
• Experience in synthesis and timing analysis
• Familiarity with EDA tools (Synopsys, Cadence, Mentor)
• Solid understanding of:
  • Digital design concepts
  • SoC architecture
  • Low‑power techniques
• Excellent communication and problem‑solving skills

Advantages:

• Knowledge of signal processing and digital communication systems
• Experience with scripting languages such as TCL and Python